1. Field of the Invention
The present invention relates to a data transfer method and an information processing apparatus having a multi processor structure with each processor having a cache memory.
2. Description of the Related Art
There are technologies, such as disclosed in Japanese Patent Application Laid-open No. 2001-101147, that enable high-speed data transfer between cache memories while preserving coherency between the cache memories in an information processing apparatus having a plurality of system boards with a plurality of central processing units (CPUs) each of which having a cache memory.
In Japanese Patent Application Laid-open No. 2001-101147, for example, when a plurality of devices (cache memories) have a transferrable data as data requested by a request source device (request source cache memory), the requested data is transferred to the request source cache memory from a cache memory that is logically nearest to the request source cache memory (for example, a cache memory that resides in the same node (system board), a cache memory in which the requested data is changed, or a most-recently selected cache memory).
Suppose that the conventional data transfer method described above is applied to an information processing apparatus that includes a plurality of CPUs each of which having cache memory, a plurality of input-output devices, a plurality of memory devices (main memories), and a plurality of system boards each of which having a system controller that manages the CPU, the input-output device, and the main memory. Here, the plurality of the system boards is connected to one another by a bus.
When the cache memories use a swap method and MOESI protocol as a cache protocol to preserve the coherency between the cache memories and when a requested data is available in the cache memory located on the same system board, the cache memory that is located on the same system board is selected. Consequently, the bus that connects the system boards is not required for the data transfer.
However, the conventional technology does not take into account the type of memory access request and/or the relation between the cache memory and the main memory. Hence, data transfer from the cache memory to the main memory could not be improved during write-back.